1. Field of the Invention
This invention relates generally to integrated circuits and, in particular, to routing wires within a programmable logic device.
2. Description of the Related Art
A programmable logic device (“PLD”) is a digital, user-configurable integrated circuit used to implement a custom logic function. For the purposes of this description, the term PLD encompasses any digital logic circuit configured by the end-user, and includes a programmable logic array, a field programmable gate array, and an erasable and complex PLD. The basic building block of the PLD is a logic element that is capable of performing limited logic functions on a number of input variables. A logic element is typically equipped with circuitry to programmably implement the “sum of products” logic, as well as one or more registers to implement sequential logic. Conventional PLDs combine together large numbers of such logic elements through an array of programmable interconnects to facilitate implementation of complex logic functions. PLDs have found particularly wide application as a result of their combined low up front cost and versatility to the user.
A variety of PLD architectural approaches arranging the interconnect array and logic elements have been developed to optimize logic density and signal routability between the various logic elements. The logic elements are arranged in groups of, for example, eight to form a larger logic array block (“LAB”). Multiple LABs are arranged in a two dimensional array and are programmably connectable to each other through global horizontal and vertical interconnect channels. Each of the horizontal and vertical channels includes one or more routing wires (“wires”). Some of the wires in each channel span a large number of LABs (e.g., 24 LABs) while other wires only span a few number of LABs (e.g., 4 LABs).
Each wire of a channel has electrical properties that include the resistance and capacitance of the wire. These electrical properties are predominantly determined by its physical length. An electrically optimum wire transmits a signal down the wire as fast as possible. There is an optimum physical length for the wire that transmits a signal down the wire as fast as possible per unit distance and hence for any distance between a source LAB and a destination LAB. Within the PLD, the wires spanning the large number of LABs and the wires spanning the few number of LABs are not electrically optimized. Electrically optimizing the wires, especially the wires spanning the large number of LABs or on a speed critical path, improve PLD performance.
For the foregoing reasons, it is desirable to have routing wires that are electrically optimum to improve PLD performance.